...
首页> 外文期刊>IEICE Electronics Express >Modified Booth encoding modulo (2n-1) multipliers
【24h】

Modified Booth encoding modulo (2n-1) multipliers

机译:修改后的Booth编码模(2n-1)乘法器

获取原文
   

获取外文期刊封面封底 >>

       

摘要

References(5) Cited-By(4) (2n-1) is one of the most commonly used moduli in Residue Number Systems. In this express, we propose a novel Booth encoding architecture. Based on the proposed Booth encoding architecture, we can design high speed and high-efficient modulo (2n-1) multipliers, which are the fastest among all known modulo (2n-1) multipliers. The performance and the efficiency of the proposed multipliers are evaluated and compared with the earlier fastest modulo (2n-1) multipliers, based on a simple gate-count and gate-delay model. These results reveal that the proposed multipliers lead to average approximately 14% faster than the fastest known modulo (2n-1) multipliers.
机译:参考文献(5)Cited-By(4)(2n-1)是残数系统中最常用的模数之一。在此表述中,我们提出了一种新颖的Booth编码架构。基于提出的Booth编码架构,我们可以设计高速高效的模(2n-1)乘法器,这是所有已知模(2n-1)乘法器中最快的。基于简单的门数和门延迟模型,对提出的乘法器的性能和效率进行了评估,并与较早的最快模(2n-1)乘法器进行了比较。这些结果表明,提出的乘法器比最快的已知模(2n-1)乘法器平均快14%。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号