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首页> 外文期刊>Applied Physics Research >Impact of Injected Charges, Clock Noise and Operational Amplifier Imperfections on the Sample and Hold (SH) Overall Performance
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Impact of Injected Charges, Clock Noise and Operational Amplifier Imperfections on the Sample and Hold (SH) Overall Performance

机译:注入电荷,时钟噪声和运算放大器缺陷对采样保持(SH)整体性能的影响

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The growing use of digital processing in analog environments underlines the importance of Analog Digital Converter (ADC) occurrence in circuitry. The quality and reliability of the conversion are closely linked to the Sample and Hold (SH) performance. Actually SH is a key component in the Analog/Digital chain. The Operational Amplifier being at the heart of the SH influences its output and subsequently impacts the reliability and quality of the conversion. In this paper we present the impact of both Operational Amplifier intrinsic characteristics and external factors such as injected charges, and clock noise on the SH overall performance. We limit our consideration to the offset and parasite capacities as the only relevant Operational Amplifier intrinsic characteristics. We’ll introduce the Operational Amplifier and SH functional characteristics then address the impact of each of these parameters on the SH output which the ADC works on. A behavioral description of the Operational Amplifier based on the Verilog-A language under Cadence approach is used. Furthermore a behavioral/analog mixed description is considered for the SH: the Operational Amplifier described behaviorally in Verilog-A is associated to analog components in Cadence libraries and CMOS switches act as SH. However this simplistic approach doesn’t reflect all the challenges involved, because it is not enough to connect a SH to ADC to flawlessly digitalize an analog signal. The SH architecture and the Operational Amplifier characteristics play also a role for a reliable sampling and therefore a good quality conversion prospect.In this study the SH performance is evaluated through its non-linearity which in turn determines the sampling accuracy a key factor for a conversion. This study is as shown that small amplitude signals are more sensible to sampling errors related to Operational Amplifier offset. Furthermore the stray capacities attenuate the SH signal output. The injected charges and the clocknoise as strongly interrelated contribute to the non-linearity of the conversion chain.
机译:在模拟环境中数字处理的使用日益增加,突显了电路中出现模拟数字转换器(ADC)的重要性。转换的质量和可靠性与采样保持(SH)性能密切相关。实际上,SH是模拟/数字链中的关键组成部分。 SH的核心运算放大器会影响其输出,进而影响转换的可靠性和质量。在本文中,我们介绍了运算放大器的固有特性和外部因素(例如注入电荷和时钟噪声)对SH整体性能的影响。我们将偏移和寄生电容作为唯一相关的运算放大器固有特性加以考虑。我们将介绍运算放大器和SH的功能特性,然后解决这些参数中的每一个对ADC所工作的SH输出的影响。在Cadence方法下,使用基于Verilog-A语言的运算放大器的行为描述。此外,还考虑了SH的行为/模拟混合描述:在Verilog-A中以行为方式描述的运算放大器与Cadence库中的模拟组件相关联,而CMOS开关充当SH。但是,这种简单的方法并不能反映所涉及的所有挑战,因为将SH连接到ADC不足以对模拟信号进行完美数字化还不够。 SH架构和运算放大器的特性对于可靠的采样也具有重要作用,因此也具有良好的转换前景。在本研究中,SH的性能是通过其非线性来评估的,这反过来又决定了采样精度是转换的关键因素。这项研究表明,小幅度信号对与运算放大器失调有关的采样误差更敏感。此外,杂散电容会衰减SH信号输出。强烈关联的注入电荷和时钟噪声会导致转换链的非线性。

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