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首页> 外文期刊>American Journal of Nanotechnology >Modelling of Digital Assisted Backend Correction Analogue to Digital Converters with Verilog-A | Science Publications
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Modelling of Digital Assisted Backend Correction Analogue to Digital Converters with Verilog-A | Science Publications

机译:Verilog-A对数字辅助后端校正模数转换器进行建模科学出版物

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> Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25?0.25, Integral Nonlinearity (INL) is -0.5?0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages."
机译: > 问题陈述:流水线架构被认为是当今数字信号处理中各种奈奎斯特模数转换器(ADC)中最适合高速和高分辨率应用的架构域。但是,随着技术的发展,管道的功耗也在不断增长。对于具有高速,高分辨率的流水线ADC,前端跟踪保持放大器和残余放大器占据了整个系统的最大功耗,因此需要新颖的方法来降低放大器的功耗。 方法:与传统的闭环放大器不同,开环放大器被用作第一级残余放大器,从而大大降低了系统功耗和设计难度。为了校正开环放大器引入的非线性误差,应用了后端数字校正。为了验证该方法的合理性和正确性并确认设计参数,使用Verilog-A建立行为模型,使用Cadence仿真工具Spectre获得结果。 结果:从行为模型的仿真结果中,我们得出数字后端校正ADC的差分非线性(DNL)为-0.25?0.25,积分非线性(INL)为-0.5?0.25,杂散自由动态范围(SFDR)为77.8dB。校正之后,系统的总谐波失真(THD)计算为73.66dB,因此,系统的有效位数(ENOB)为11.78位。 结论:数字辅助后端校正是降低流水线ADC功耗的一种新颖方法,在混合信号系统设计中具有重要意义。使用开环放大器代替传统的闭环放大器可以有效地降低设计难度和设计过程。本文仅将第一级残余放大器更改为开环,并且这种替换也可以在跟踪和保持电路及后续级中复制。”

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