基于Verilog-A的流水线型ADC数字校正技术仿真平台

摘要

为了对流水线型ADC数字校正技术进行研究,提出了一种基于Verilog-A的行为级仿真平台.在该平台中,采用Verilog-A语言对流水线型ADC中各个组成模块进行建模、采用Volterra级数对系统误差进行模拟、采用Verilog语言对数字校正算法进行建模.应用此平台,结合一种确定性的数字校正技术对一个12位分辨率,1.5位每级结构,40MHz采样速度的流水线型ADC进行了仿真.在芯片设计之前使用该平台进行仿真,不仅能够有效地缩短流水线型ADC数字校正技术的硬件设计周期,还提高了校正算法开发的灵活性和实用性,从而对进一步提高流水线型ADC的性能、降低功耗起到重要的促进作用,具有很高的实用价值.%To research pipeline ADC digital calibration technique, a Verilog-A based behavioral simulation platform is proposed. In this platform, Verilog-A language is adopted to mimic the modules in pipeline ADC, Volterra series theory is applied to imitate system error, Verilog language is employed to module digital algorithm. Applying this platform, a 10 bits, 1.5 per stage structure, 50 MHz sample speed background calibration pipeline ADC with a deterministic calibration algorithm is simulated.Applying this platform in simulation before chip design can not only reduce pipeline ADC digital calibration technique design cycle,but also improve calibration algorithm developing flexibility and practicability.Thus,pipeline ADC performance can be further improved, and power consumption can be further reduced,so it has high practical value.