Optimum design of phase opposition disposition pulse width modulation logic circuit for switching seven level cascaded half bridge inverter

摘要

Theevolution of multilevel inverters (MLIs) has made it possible to extract power from direct current (DC) sources to alternating current (AC) power. This paper presents the design of a novel phase opposition disposition pulse width modulation scheme (PODPWM) logic circuit for a conventional single phase seven level cascaded H-Bridge (CHB) inverter using Matla b/Simulink. The minimum switching logic circuit for the single phase seven level CHB inverter was obtained by modeling the logic equations that could be used with any number of levels depending on the number of modulating and carrier signals involved. The reduction in total harmonic distortion (THD) of the output voltage for the MLI using low switching frequency at different modulation indixes is also investigated. The logic equations have made it easier to design a PODPWM circuit for any CHB inverter and the logic gates designed gave an optimum THD value of 16.73 % at modulation index of 0.20.