The Design of Three Phase Programmable Testing Power Based on CPLD_DSP

摘要

A design of three phases programmable testing power program-controlled based on CPLD_DSP was introduced in the paper. RAM was driven and six DDS were generated in CPLD. RAM was driven and six DDS (three voltage signal and three current signal) were generated in CPLD. The six DDS signal was used as based signal of testing power. CPLD was programmed to control serial D/A chip named LTC1595B to adjust the value of voltage and current. Voltage signal and current signal were collected and computed and closed loop by DSP. After testing, the output frequency resolution of the system achieved 0.001Hz.The voltage and current control precision achieved 0.02%.