Study of pattern area of logic circuit with tunneling field-effect transistors

Yu Hiroshima; Ryosuke Suzuki; Shigeyoshi Watanabe

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Study of pattern area of logic circuit with tunneling field-effect transistors

机译：隧穿场效应晶体管的逻辑电路图形面积研究

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《Contemporary Engineering Sciences 》 |2013年第6期| 共12页
作者
Yu Hiroshima; Ryosuke Suzuki; Shigeyoshi Watanabe;
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1. High-Speed and Low-Power Source-Coupled Field-Effect Transistor-Logic-Type Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology [J] . Hyungtae KIM, Seongjin YEON, Kwangseok SEO Japanese journal of applied physics . 2008 ,第4issue2期

机译：利用谐振隧穿二极管/高电子迁移率晶体管集成技术的高速和低功率源耦合场效应晶体管逻辑型不归零延迟触发器电路
2. Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits [J] . Min-Chul Sun, Sang Wan Kim, Hyun Woo Kim, Japanese journal of applied physics . 2012 ,第4ISSUE2期

机译：超低功耗逻辑电路的薄型双栅垂直沟道隧穿场效应晶体管的设计
3. Carbon Nanotube Field-Effect Transistors for Use as Pass Transistors in Integrated Logic Gates and Full Subtractor Circuits [J] . Li Ding, Zhiyong Zhang, Tian Pei, ACS nano . 2012 ,第5期

机译：碳纳米管场效应晶体管，用作集成逻辑门和完整减法器电路中的通过晶体管
4. Flexible Logic Circuits by using Van Der Waals Contacted Graphene Field-Effect Transistors [C] . Fengyuan Liu, Nivasan Yogeswaran, William Navaraj, IEEE International Symposium on Circuits and Systems . 2019

机译：使用Van Der Waals接触式石墨烯场效应晶体管的灵活逻辑电路
5. Design, fabrication and characterization of N-channel InGaAsP-InP based inversion channel technology devices (ICT) for optoelectronic integrated circuits (OEIC): Double heterojunction optoelectronic switches (DOES), heterojunction field-effect transistors (HFET), bipolar inversion channel field-effect transistors (BICFET) and bipolar inversion channel phototransistors (BICPT). [D] . Tan, Eugene. 1998

机译：基于N沟道InGaAsP-InP的倒置通道技术器件（ICT）的设计，制造和表征，用于光电集成电路（OEIC）：双异质结光电开关（DOES），异质结场效应晶体管（HFET），双极倒置沟道场-效应晶体管（BICFET）和双极型反向沟道光电晶体管（BICPT）。
6. Study on Single Event Effect Simulation in T-Shaped Gate Tunneling Field-Effect Transistors [O] . Chen Chong, Hongxia Liu, Shulong Wang, 2021

机译：T形闸门隧道场效应晶体管单事件效应模拟研究
7. Study of Pattern Area of Logic Circuit with Tunneling Field-Effect Transistors [O] . Yu Hiroshima, Shigeyoshi Watanabe 2014

机译：用隧道场效应晶体管研究逻辑电路的图形区域

Study of pattern area of logic circuit with tunneling field-effect transistors

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