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Design and evaluation of SiC multichip power module with low and symmetrical inductance

机译:低对称电感SiC多芯片功率模块的设计与评估

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Compared to silicon devices, silicon carbide (SiC) devices have much lower C oss and Q g ; they can switch at much higher speed, SiC power modules are thus more sensitive to stray parameters. Large stray inductance may result in high voltage spikes and cause severe electro-magnetic interference (EMI) issues; unbalanced stray inductance may contribute to uneven current sharing between parallel devices. Low and symmetrical inductance is a necessity to fully utilise the superior characteristics of SiC devices. This paper first studies the current sharing and voltage spike mechanisms of multichip power modules (MCPMs). Stray inductance distribution, current sharing as well as voltage spikes under different direct bonded copper (DBC) layout conditions are investigated using finite element modelling software. A round symmetrical DBC layout is then proposed. Compared with conventional ones, the proposed structure is symmetrical in stray inductance distribution; thus improving the consistency among chips. To reduce the total equivalent stray inductance and tackle the voltage spike problem, this study further presents an improved 3D structure on the basis of the round symmetrical DBC. The stray inductance extraction and double pulse simulation results verify the effectiveness of the improved 3D structure in current sharing as well as voltage spike reduction.
机译:与硅器件相比,碳化硅(SiC)器件具有低得多的C oss 和Q g ;它们可以以更高的速度切换,因此SiC电源模块对杂散参数更加敏感。大的杂散电感可能会导致高压尖峰并引起严重的电磁干扰(EMI)问题;杂散电感的不平衡可能会导致并联器件之间的电流分配不均。低且对称的电感是充分利用SiC器件优异特性的必要条件。本文首先研究了多芯片电源模块(MCPM)的均流和电压尖峰机制。使用有限元建模软件研究了不同直接键合铜(DBC)布局条件下的杂散电感分布,均流以及电压尖峰。然后提出了一个圆形对称的DBC布局。与常规结构相比,该结构在杂散电感分布上是对称的。从而提高了芯片之间的一致性。为了减少总等效杂散电感并解决电压尖峰问题,本研究在圆形对称DBC的基础上进一步提出了一种改进的3D结构。杂散电感提取和双脉冲仿真结果验证了改进的3D结构在均流以及降低电压尖峰方面的有效性。

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