IC Outlier Identification Using Multiple Test Metrics

摘要

WITH ADVANCES in semiconductor manufacturing processes, ICs become faster, more powerful, and more densely packed. This in turn makes testing difficult, especially for deep-submicron chips (http://public.itrs.net). Engineers use parametric tests to evaluate different IC parameters like speed or leakage current (I_(DDQ)). If a parameter is outside a predetermined limit or threshold, the chip is considered defective. For example, a chip can operate too slowly (a delay failure) or consume excessive I_(DDQ). Engineers usually determine the pass/fail threshold by taking a sample of chips from the initial production for characterization. Alternatively, they can build device models and determine a threshold through simulation. Chips that fail only parametric tests do not meet their specifications completely, but are functional. However, manufacturers can reject such chips for reliability reasons. With the reduction in transistor geometries, precise process control of manufacturing becomes more difficult. This leads to variation in transistor parameters, both within a chip and within a wafer (across chips). This results in a large spread in fault-free parameter values. For example, I_(DDQ) increases exponentially as you scale down transistors. As a result, setting the pass/fail threshold becomes difficult because the overlap between fault-free and faulty distributions invariably results in yield loss and/or test escapes. If you plot a distribution of test parameters for different chips, the defective chips appear as outliers in the tail of the distribution. Screening these chips is therefore, in principle, similar to statistical outlier rejection. Since statistical outlier rejection is a well-researched topic, this opens up a wide variety of statistical methods for application to VLSI testing. This article presents an overview of the application of outlier identification methodology for VLSI test, using industrial test data.