AS DEVICES SHRINK toward the nanometer scale, on-chip interconnects are becoming a critical bottleneck in meeting performance and power consumption requirements of chip designs. Industry and academia recognize the interconnect problem as an important design constraint, and, consequently, researchers have proposed packet-based on-chip communication networks, known as networks on chips (NoCs), to address the challenges of increasing interconnect complexity. NoC designs promise to deliver fast, reliable, energy-efficient communication between on-chip components. Because most application traffic is bursty in nature, packet-switched networks are suitable for NoCs.
展开▼
