NETWORK ON CHIP ROUTER AND TIMING ERROR RECOVERY METHOD THEREOF

摘要

A network-on-chip router and a timing error correction method thereof are disclosed. The NoC router according to an embodiment of the present specification is a NoC router constituting a network-on-chip (NoC), one or more arbiters consisting of one or more stages, among the one or more stages Any one includes an error detection unit of an input signal and a pass gate for blocking at least a portion of a signal allocated to the one or more arbiters based on a signal received from the error detection unit.