An FPGA prototype of a forward error correction (FEC) decoder for ATSC digital TV

摘要

The paper presents the development of an FEC decoder for ATSC digital TV. An FEC encoder/decoder system has been first built up for studying the performance of the FEC decoder and also for providing testing vectors for the architecture design. The architecture of the FEC decoder, including trellis decoder, de-interleaver, Reed-Solomon (RS) decoder and de-randomizer is then designed. The decoder has been prototyped in FPGAs and verified using an FPGA board. The FEC decoder can achieve the threshold of visibility (TOV) at 14.9 dB and 18.8 dB in the cases without and with NTSC rejection filter respectively.