Investigating the effect of binder and aggregate application rates on performance of chip seals via digital image processing and sweep tests

摘要

Relationship between the internal microstructure of chip seals (e.g., the percent embedment, aggregate shape and orientation) and their performance is not well understood. In an effort to improve understanding of the relationship between binder/aggregate application rates and the microstructure of chip seals, image processing and analysis techniques were developed to quantify percent embedment (PE) and aggregate orientation. A new parameter called "Effective Percent Embedment" was introduced for improved quantification of the effect of application rates on aggregate loss during the sweep test It was observed that aggregates orient on their flattest side as the binder application rate increases and aggregate application rate decreases. These results are expected to serve as a basis for performance based chip seal design guidelines focusing on compacted chip seal aggregate structure. (C) 2019 Elsevier Ltd. All rights reserved.