Compiler driven data layout optimization for regular/irregular array access patterns

摘要

Memory access patterns on multiprocessor systems-on-chip (MPSoC) are complex enough that they often defeat hardwired caching strategies. Instead of hardwired caches, these systems use scratch pad memory (SPM), acting as a software-controlled cache on each individual processor.rnDecisions on data placement in SPMs are more straightforward when access patterns in an application are regular than when they are irregular (regular versus irregular applications). What this paper presents are solutions to two problems in the context of irregular applications: how to use profile (runtime) statistics that identify parts of data arrays for copying into SPMs, such that performance and energy consumption are improved, and how to maximize utilization of the SPM resources.