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Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics

机译:使用等量线评估不对称多核片上系统的容错能力

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The end of Dennard scaling has promoted low power consumption into a first-order concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, reliability. These limitations would make them unsuitable for HPC systems and datacenters. To demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM's big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the study describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.
机译:Dennard扩展的终结已将低功耗提升为计算系统的首要考虑因素。然而,当在性能受限的环境中使用时,诸如电压和频率缩放之类的常规功率节省方案已达到其极限。在维持未来处理器性能的同时,还需要新技术来打破壁垒。低功耗嵌入式处理器和近阈值电压计算(NTVC)已被提出作为解决未来计算系统中的电源壁问题的可行解决方案。不幸的是,这些技术也可能会损害每核的性能以及NTVC的可靠性。这些限制将使其不适用于HPC系统和数据中心。为了证明新兴的低功耗处理技术可以有效替代传统技术,本研究依赖于ARM的big.LITTLE处理器作为实际平台和仿真平台,以及CG求解器的最新实现。特别是对于NTVC,该研究描述了基于有效算法的容错方案如何保持超低压运行的功率和能量收益。

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