机译:实值串行流水线FFT的节能VLSI架构
IIT Guwahati Dept Elect & Elect Engn Gauhati 781039 India;
field programmable gate arrays; application specific integrated circuits; VLSI; fast Fourier transforms; digital signal processing chips; flip-flops; pipeline processing; energy-per-sample; energy efficient VLSI architecture; real-valued serial; energy-efficient serial; fast Fourier; data mapping scheme; normal order input-output; post-processing stage; computational workload; hardware resources; mathematical derivations; relatively lower hardware complexity; quarter operation; complex multiplier; clock cycle; relatively lower power; merged unit; butterfly computation; data re-ordering; half-butterfly operation; hardware usage; field programmable gate array results; 1024-points FFT computation;
机译:常规I / O阶流水线FFT设计的高效VLSI架构
机译:用于实数据上FFT的可扩展就地计算的面积,延迟,能源高效的VLSI架构
机译:具有实数据路径的实值FFT和Hermitian对称IFFT的流水线架构
机译:用于实值FFT的高性能无乘法器串行流水线VLSI架构
机译:使用实时计算的低密度奇偶校验解码器的面积和节能VLSI架构。
机译:使用通用Hebbian算法的高效多通道Spike排序VLSI架构
机译:适用于折叠流水线复杂FFT内核的高效无乘法器VLSI架构