Efficient mapping of FFT to a reconfigurable parallel and pipeline data flow machine

摘要

A system comprises first and second local memory banks; and a reconfigurable ALU array having multiple configurations including: a first for performing an inverse butterfly operation, a second for performing a multiplication operation, a third for performing parallel subtraction and addition, and a fourth for performing an inverse N-point shuffle. The ALU array may obtain input for the inverse butterfly operation from the first bank and store output in the second bank. The ALU array may obtain input for the multiplication operation from the second bank and store output in the first bank. The ALU array may obtain input for the parallel subtraction and addition operation from the first bank and store output in the second bank. The ALU array may obtain input for the N-point inverse shuffle from the second bank and store output in the first bank. The system may further comprise a bit reversal block.