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A Measurement Method on Nanoscale Thickness of the Ti Barrier Layer of TSV Structure for 3-D IC

机译:用于3-D IC的TSV结构的Ti阻挡层的纳米级厚度的测量方法

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摘要

As the characteristic dimension of an integrated circuit (IC) continuously scales down, together with the requirements of low power consumption, multiple functionality, and cost effectiveness, the conventional IC transforms into a 3-D IC. Through-silicon via (TSV) is a promising and preferred way to realize the reliable interconnection for a 3-D IC. Thus, accurate measurement of the critical structural parameters plays an important role in securing the integrity and reliability of TSV. In this paper, a novel image-processing-based measurement method is proposed to measure the barrier layer thickness and step coverage of TSV. Since the thickness of the barrier layer is generally less than 100 nm, which is a drawback of the conventional SEM method, we used the material information from SEM as well as structural prior of TSV to infer the barrier layer thickness on nanoscale. In addition, we further achieved the step coverage of thin films in TSV using the proposed measurement method.
机译:随着集成电路(IC)的特性尺寸不断缩小,以及对低功耗,多功能性和成本效益的要求,常规IC转变为3-D IC。硅通孔(TSV)是实现3-D IC可靠互连的一种有希望的首选方法。因此,关键结构参数的准确测量在确保TSV的完整性和可靠性方面起着重要作用。本文提出了一种基于图像处理的新型测量方法,用于测量势垒硅通孔的势垒层厚度和台阶覆盖率。由于阻挡层的厚度通常小于100 nm,这是常规SEM方法的一个缺点,因此我们使用SEM的材料信息以及TSV的结构先验来推断纳米级的阻挡层厚度。此外,我们使用所提出的测量方法进一步实现了TSV中薄膜的阶梯覆盖。

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