Design and realisation of a fractional-order sinusoidal oscillator

摘要

In this work, a new fractional-order sinusoidal oscillator is proposed. The proposed oscillator consists of one fractional-order all-pass filter and one fractional-order lossless integrator blocks. In order to emulate fractional-order capacitors, three different approximation methods the R-C pair, Matsuda and Oustaloup are employed and the results are compared. Three sinusoidal voltage signals with different phases that are controlled by fractional orders are provided by the proposed oscillator topology that is not possible for the classical integer-order case. Grounded passive components are used in the introduced oscillator circuit. Additionally, the output voltage signals are available at the low impedance terminal W of AD844ANs. Moreover, the time constant of the fractional-order all-pass filter can be adjusted accurately by means of second resistor R-x in the all-pass filter section. In addition to the simulation results, the proposed fractional oscillator is also implemented to verify the oscillator circuit experimentally. For the case of fractional orders alpha = 1 and beta = 0.5, the measurement results are 10.3 kHz, 43.22 degrees and 67.99 degrees, respectively, while the desired values are 10 kHz, 45 degrees and 67.36 degrees, respectively.