Inherently linear capacitor error-averaging techniques forpipelined A/D conversion

摘要

New passive capacitor mismatch error-averaging techniques fornpipelined analog-to-digital conversion is presented. The excellentnlinearity inherent to the architecture effectively eliminates thencapacitor matching requirement that prevents a conventional monolithicnpipelined analog-to-digital converter from reaching a 10-bit and abovenintegral nonlinearity (INL) without trimming and/or calibration.nSimulation results confirm the observation and a case of 14 bit INLnrealized by 7 bit capacitor matching is shown. The relaxed matchingnrequirement enables the scale-down of the capacitor sizes to that of thenKT/C limit. As a result, great reductions in both power consumption andnchip area can be achieved