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A low power VLSI architecture for mesh-based video motion tracking

机译:用于基于网格的视频运动跟踪的低功耗VLSI架构

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This paper proposes a low-power very large-scale integration (VLSI) architecture for motion tracking. It uses a hierarchical adaptive structured mesh that generates a content-based video representation. The proposed mesh is a coarse-to-fine hierarchical two-dimensional mesh that is formed by recursive triangulation of the initial coarse mesh geometry. The structured mesh offers a significant reduction in the number of bits that describe the mesh topology. The motion of the mesh nodes represents the deformation of the video object. The architecture consists of motion estimation and motion compensation units. The motion estimation architecture generates a progressive mesh code and the motion vectors of the mesh nodes. It reduces the power consumption, uses a simpler approach for mesh construction, approximates the mesh nodes motion vector by using the three step search algorithm and uses a parallel motion estimation core to evaluate the mesh nodes motion vectors. Moreover, it maximizes the lifetime of the internal buffers. The motion compensation architecture uses a multiplication-free algorithm for affine transformation, which significantly reduces the complexity of the motion compensation architecture. Moreover, using pipelined affine units contributes to the power savings. The video motion compensation architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame. It implements parallel threads in which each thread implements a pipelined chain of scalable affine units. This motion compensation algorithm allows the use of one simple warping unit to map a hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. The processor uses a memory serialization unit, which interfaces the memory to the parallel units. The architecture has been prototyped using top-down low-power design methodology. The performance analysis shows that this processor can be used in online object-based video applications such as in MPEG and VRML.
机译:本文提出了一种用于运动跟踪的低功耗超大规模集成(VLSI)架构。它使用分层的自适应结构化网格,该网格生成基于内容的视频表示。所提出的网格是通过对初始粗网格几何形状进行递归三角剖分而形成的从粗到细的分层二维网格。结构化网格大大减少了描述网格拓扑的位数。网格节点的运动表示视频对象的变形。该架构包括运动估计和运动补偿单元。运动估计架构生成渐进式网格代码和网格节点的运动矢量。它降低了功耗,使用了一种更简单的方法来构建网格,通过使用三步搜索算法来近似网格节点运动矢量,并使用并行运动估计核心来评估网格节点运动矢量。而且,它可以最大限度地延长内部缓冲器的寿命。运动补偿架构使用无乘法算法进行仿射变换,从而大大降低了运动补偿架构的复杂性。此外,使用流水线仿射单元有助于节省功率。视频运动补偿体系结构处理参考帧,网格节点和运动矢量以预测视频帧。它实现了并行线程,其中每个线程都实现了可伸缩仿射单元的流水线链。这种运动补偿算法允许使用一个简单的翘曲单元来映射层次结构。仿射单元可以在任何层次的层次网格上独立扭曲贴图的纹理。处理器使用内存序列化单元,该单元将内存与并行单元接口。该架构已使用自上而下的低功耗设计方法进行了原型设计。性能分析表明,该处理器可用于基于对象的在线视频应用程序,例如MPEG和VRML。

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