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An All-Digital Despreading Clock Generator

机译:全数字解扩时钟发生器

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摘要

An all-digital despreading clock generator (DSCG) is presented. For an input spread-spectrum clock with a modulation frequency of 15-40 kHz and a down spreading of 5000 ppm, this DSCG successfully realizes a nonspread-spectrum clock. It is fabricated in a 0.18- μm CMOS process. For an input spread-spectrum clock of 1.5 GHz with a down spreading of 5000 ppm and a modulation frequency of 30 kHz, the measured root-mean-square and peak-to-peak jitters of this DSCG are 2.94 and 22.78 ps, respectively. The active area including input/output buffers is 0.84 mm2. Its power consumption is 19.8 mW, for a supply of 1.8 V.
机译:提出了一种全数字解扩时钟发生器(DSCG)。对于调制频率为15-40 kHz,向下扩展为5000 ppm的输入扩频时钟,该DSCG成功实现了非扩频时钟。它采用0.18-μmCMOS工艺制造。对于1.5 GHz的输入扩频时钟,向下扩展为5000 ppm,调制频率为30 kHz,此DSCG的实测均方根抖动和峰峰值抖动分别为2.94 ps和22.78 ps。包括输入/​​输出缓冲区的有效区域为0.84 mm 2 。对于1.8 V的电源,其功耗为19.8 mW。

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