A 2.4-GHz All-Digital PLL With a 1-ps Resolution 0.9-mW Edge-Interchanging-Based Stochastic TDC

摘要

A 2.4-GHz all-digital phase-locked loop (ADPLL) for Zigbee application is presented. A stochastic time-to-digital converter (STDC) with an edge-interchange circuit (EIC) is proposed. The rising edges of the two input clocks of STDC are cyclically interchanged by EIC, which achieves dynamic element matching and doubles the equivalent number of arbiters in STDC. The frequency resolution of the -based digitally controlled oscillator is improved by the tiny unit capacitor and the high-speed dithering. The proposed ADPLL has been implemented in a 0.13- CMOS technology. The measurement results show a 9-mW total power consumption, in which the proposed 1-ps-resolution STDC only consumes 0.9 mW. The in-band and out-band phase noise are −83.0127 dBc/Hz at 10 kHz and −118.95 dBc/Hz at 1 MHz. The root-mean-square jitter and peak-to-peak jitter are 4.6 and 25.7 ps, respectively.