A 0.4-to-1 V Voltage Scalable $Delta Sigma $ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS

摘要

This brief presents a two-step hybrid integrator (TSHI) that can operate at a wide supply voltage range, which is demonstrated with a third-order ΔΣ analog-to-digital converter (ADC). The proposed TSHI consists of a zero-crossing-detector (ZCD)-based integrator and an inverter-based integrator. In the coarse-integration step, the ZCD-based integrator performs a fast integration without concern for overshoot or detection delay issues. In the fine-integration step, the inverter-based integrator performs the residual integration with high accuracy. Hence, the TSHI provides fast and accurate integration process. In addition, the TSHI supports trade-off between voltage-scalable bandwidth and power consumption for an energy efficient operation of Internet-of-Things sensor nodes, owing to the scalable operation of the ZCD and inverter. The proposed ΔΣ ADC is fabricated in a 65-nm LP CMOS process, and the active area is 0.38 mm2. The fabricated ADC operates at supply voltages from 0.4 to 1 V. Depending on the supply voltage and sampling frequency, the power consumption and bandwidth of the ADC can be scaled from 12.7 to 948 μW and from 7.5 to 400 kHz, respectively. The ADC maintains an SNDR higher than 60 dB within the operating supply range.