机译:在40 nm CMOS中的42 fJ / Step-FoM两步基于VCO的Delta-Sigma ADC
Graduate School at Shenzhen, Tsinghua University, Shenzhen, China;
Clocks; Delays; Gain; Logic gates; Quantization (signal); Transistors; Voltage-controlled oscillators; Anglog-to-digital converter; VCO-based ADC; VCO-based quantizer; delta-sigma ADC; distortion cancellation; high-banwidth; highly-digital; intrinsic DEM; intrinsic anti-aliasing; low-power; nonlinearity mitigation; open-loop; power-efficient; time-domain ADC; two-step; voltage swing reduction;
机译:具有35-fJ / Step FoM的40MHz带宽0-2 MASH VCO的Delta-Sigma ADC
机译:基于二阶VCO的CTΔΣADC,在40-NM CMOS中使用改进的DPLL结构
机译:基于节能开关和共享环形放大器的12.1 fJ / Conv.-Step 12b 140 MS / s 28-nm CMOS流水线SAR ADC
机译:一个40MHz-BW两步开环基于VCO的ADC,在40nm CMOS中具有42fJ /步的FoM
机译:采用65nm CMOS技术的基于时间的低功耗,低失调5位1 Gs / S闪存ADC设计
机译:低功耗CMOS的霍尔传感器结构简单使用双取样Delta-Sigma ADC
机译:6.94-FJ /转换 - 步骤12位100-MS / S异步SAR ADC在65-NM CMOS中利用分割CDAC