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首页> 外文期刊>Circuits and Systems II: Express Briefs, IEEE Transactions on >Energy-Efficient Hardware Architecture of Self-Organizing Map for ECG Clustering in 65-nm CMOS
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Energy-Efficient Hardware Architecture of Self-Organizing Map for ECG Clustering in 65-nm CMOS

机译:用于65nm CMOS的ECG群集的自组织映射的节能硬件架构

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摘要

An energy-efficient hardware architecture of a self-organizing map (SOM) for ECG clustering is proposed. It detects an R-peak, reconstructs the QRS complex around it, and clusters the complex by calculating the Euclidean distance between the complex and the weight vectors of each cell in the SOM network (i.e., 5×5 cells). In the operation mode, the cluster ID related to the minimum Euclidean distance is provided, while the tagged weight vectors are updated in the learning mode. The proposed SoC is 1735 × 1020 μm in CMOS 65-nm LP, and it consumes 5.853 mW at VDD = 1.2 V.
机译:提出了一种用于ECG聚类的自组织映射(SOM)的节能硬件体系结构。它检测一个R峰,重建其周围的QRS复数,并通过计算SOM网络中每个单元格(即5×5单元格)的复数和权重向量之间的欧式距离来对复数进行聚类。在操作模式下,提供与最小欧几里得距离有关的聚类ID,而在学习模式下更新标记的权重向量。拟议的SoC在CMOS 65-nm LP中为1735×1020μm,在VDD = 1.2 V时功耗为5.853 mW。

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