Logic Operation of HTS SFQ Logic Family

摘要

A high-$T_{c}$ superconducting (HTS) single-flux-quantum (SFQ) logic family including an and gate, an or gate, and an inverter was designed. The circuit parameters were optimized for a Josephson junction's critical current density, which may change due to a temperature change or insufficient run-to-run reproducibility of the fabrication process. New circuit design layout rules were implemented to improve $I_{c}$ uniformity. As a result, all circuits were successfully tested and show at least $pm$40% critical current density operational margins. An effect of the parasitic capacitance formed by a junction electrode and a ground plane on the operating margins of the and gate was investigated by numerical simulation. Test circuits were fabricated using $hbox{YBa}_{2} hbox{Cu}_{3}hbox{O}_{7 - delta}$ ramp-edge junction technology and were operated at temperatures higher than 30 K. Bias current margins were also measured, and they found to be close to the simulated ones.