Band bending effect induced by gate voltage on the charge loss behavior of charge trap flash memory devices

摘要

We found that the polarity of the gate voltage (V_g) during the retention characteristics for a SiO_2/Si_3N_4/Al_2O_3 (ONA) stack can affect the charge loss direction, due to band bending. Positive V_g could induce electron de-trapping through Al_2O_3, while a negative V_g could induce the same through SiO_2. Consequently, the charge loss rates exhibited a hairpin curve with V_g. We clearly observed that increases of the SiO_2 thickness of the ONA stack induced negative shifts of hairpin curve. This result suggests that the dominant charge loss path could be changed from SiO_2 to Al_2O_3 by increasing the SiO_2 thickness without V_g.