Depth localization of positive charge trapped in silicon oxynitride field effect transistors after positive and negative gate bias temperature stress

摘要

Positive charge trapped in the SiO(N) gate dielectric of deeply-scaled p-channel metal-oxide-semiconductor field-effect transistors is observed after both negative and positive gate bias temperature stress. Emission of elementary trapped charges is demonstrated and analyzed through the quantized threshold voltage transients observed after stress. The magnitude distribution of the threshold voltage steps is used to estimate the depth of the traps in the gate dielectric to be about 0.5 nm from the injecting silicon-dielectric interface in both cases.