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Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer

机译:与具有薄ZnO界面层的n型Ge接触时的费米能级钉扎和低电阻率

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摘要

We report low resistance Ohmic contacts on n-Ge using a thin ZnO interfacial layer (IL) capped with Ti. A 350 ℃ post metallization anneal is used to create oxygen vacancies that dope ZnO heavily n-type (n~+). Rectifying Ti-Ge contacts become Ohmic with 1000× higher reverse current density after insertion of n~+-ZnO IL. Specific resistivity of ~ 1.4 × 10~(-7) Ωm~2 is demonstrated on epitaxial n~+-Ge (2.5 × 10~(19) cm~(-3)) layers. Low resistance with ZnO IL can be attributed to (a) low barrier height from Fermi-level unpinning, (b) good conduction band alignment between ZnO and Ge, and (c) thin tunneling barrier due to the n~+ doping.
机译:我们报道了使用覆盖有Ti的薄ZnO界面层(IL)在n-Ge上的低电阻欧姆接触。在350℃的金属化后退火中产生氧空位,这些空位使ZnO重掺杂为n型(n〜+)。插入n〜+ -ZnO IL后,整流的Ti / n-Ge接触变为欧姆型,反向电流密度提高1000倍。在外延n〜+ -Ge(2.5×10〜(19)cm〜(-3))层上显示出约1.4×10〜(-7)Ωm〜2的电阻率。 ZnO IL的低电阻可归因于(a)费米能级解除钉扎产生的低势垒高度,(b)ZnO和Ge之间的良好导带对准以及(c)由于n〜+掺杂而形成的薄隧道势垒。

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  • 来源
    《Applied Physics Letters》 |2012年第18期|182105.1-182105.5|共5页
  • 作者单位

    Center of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India;

    Center of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India;

    Center of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India;

    Center of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India;

    Applied Materials Inc., Santa Clara, California 94085, USA;

    Applied Materials Inc., Santa Clara, California 94085, USA;

    Applied Materials Inc., Santa Clara, California 94085, USA;

    Center of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India;

    Center of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India;

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