Effects of sidewall etching on electrical properties of SiO_x resistive random access memory

摘要

The electroforming voltages (V_(ef)) of silicon oxide resistive random access memory devices with oxide sidewall etched to different degrees are compared. The results show that the V_(ef) is significantly reduced when more sidewall area is formed, and V_(ef) of around 17 V is achieved in devices with maximum sidewall area. Plausible electroforming and state switching mechanisms are discussed using a filament-gap model. Endurance measurements up to 10~7 pulse cycles are compared for different device types. An external series resistance may be helpful for decreasing voltage stress during pulsed cycling to help enable device survival beyond 10~7 pulse cycles.