首页> 外文期刊>Advanced Packaging, IEEE Transactions on >Channel Coding For High-Speed Links: A Systematic Look at Code Performance and System Simulation
【24h】

Channel Coding For High-Speed Links: A Systematic Look at Code Performance and System Simulation

机译:高速链路的信道编码:系统地研究代码性能和系统仿真

获取原文
获取原文并翻译 | 示例
           

摘要

While channel coding is a standard method of improving a system's energy efficiency in digital communications, its practice does not extend to high-speed links. Increasing demands in network speeds are placing a large burden on the energy efficiency of high-speed links and render the benefit of channel coding for these systems a timely subject. The low error rates of interest and the presence of residual intersymbol interference (ISI) caused by hardware constraints impede the analysis and simulation of coded high-speed links. Focusing on the residual ISI and combined noise as the dominant error mechanisms, this paper analyzes error correlation through concepts of error region, channel signature, and correlation distance. This framework provides a deeper insight into joint error behaviors in high-speed links, extends the range of statistical simulation for coded high-speed links, and provides a case against the use of biased Monte Carlo methods in this setting. Finally, based on a hardware test bed, the performance of standard binary forward error correction and error detection schemes is evaluated, from which recommendations on coding for high-speed links are derived.
机译:尽管信道编码是提高系统数字通信能量效率的标准方法,但其实践并未扩展到高速链路。对网络速度的日益增长的需求给高速链路的能量效率带来了沉重负担,并使这些系统的信道编码优势成为及时的主题。感兴趣的低错误率以及由硬件约束导致的残留符号间干扰(ISI)的存在阻碍了编码高速链路的分析和仿真。着眼于残留ISI和组合噪声作为主要的误差机制,本文通过误差区域,通道签名和相关距离的概念分析了误差相关性。该框架提供了对高速链接中的联合错误行为的更深入的了解,扩展了编码高速链接的统计仿真的范围,并提供了在这种情况下避免使用有偏的蒙特卡洛方法的案例。最后,在硬件测试平台的基础上,评估了标准二进制前向纠错和错误检测方案的性能,从中得出了有关高速链路编码的建议。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号