一种新的基于FPGA的雷达视频压缩方法

摘要

According to the characteristics of radar video image that the resolutian is high and the information of the aim target is alvays included in high frequenly details a high resolution radar video image compression scheme is proposed and implemented on FPGA. The key modules as DCT,quantification, and encoder are designed respectively. The scheme is accomplished in a Stratix ⅣGX EP4SGX230KF40C4 chip. The experimental results show that the utilization is low and the image quality after compressed is good with the processing speed is higher than 50 f/s for 1 600 ×1200 resolution video image which meets the requirements of high resolution radar video real-time compression.%针对目前雷达视频分辨力较高、目标信息多包含在高频细节部分的特点,设计并实现了一种基于FPGA的高分辨力雷达视频压缩方案.该方案分别对DCT、量化、编码等核心处理模块分别进行优化设计,以适应雷达视频压缩的需求.在1片Stratix ⅣGX EP4SGX230KF40C4芯片上进行验证,结果表明,该设计方案资源占用率低,压缩后图像质量较好,对于1600×1200分辨力的视频处理速度可达50f/s(帧/秒)以上,满足高分辨力雷达视频实时压缩的要求.