基于FPGA的低功耗高精度DPWM设计

摘要

提出了一种基于FPGA实现低功耗、高分辨力数字脉冲调制(DPWM)的设计方案.该方案在获得高分辨力DPWM的同时降低了对系统时钟频率的要求.该方法充分利用了数字时钟管理器(DCM)的倍频及移相功能,而且使DCM模块只在开关周期的1/16工作从而减少系统的功耗.在系统时钟频率为16 MHz,开关频率为1 MHz,实现了11位分辨力的DPWM并通过了FPGA对其的仿真及验证.%A design scheme of Digital Pulsewidth Modulator( DPWM) based on FPGA with low power consumption and high resolution is presented. This scheme realizes high resolution DPWM and reduces requirement of system clock frequency at the same time. The method fully utilizes frequency duplication and phase shift functions of Digital Clock Managers(DCM) ,and makes DCM block just work at 1/16 of the switch cycle,and then decreases power dissipation. This paper achieves DPWM of 11 bit resolution and passes the simulation and verification conducted in FPGA in the case that the system clock frequency is 16 MHz and the switch frequency is 1 MHz.