基于FPGA的CMOS图像传感器LUPA-4000时序设计

摘要

This paper describes the method to design the timing sequence for the CMOS image sensor LUPA-4000.The timing sequence includes the design of system time adjustment, parallel working, multi-slope integration, NDR (Non-destructive readout) and adjustable integration time. The design is implemented by FPGA (Field-Programmable Gate Array) and the test experiments show its good and stable performance. The LUPA- 4000 which is driven by the design is fit for space exploration and dynamic tracking of dark object.%文章在分析CYPRESS公司CMOS图像传感器LUPA-4000驱动时序的基础上．采用现场可编程逻辑阵列（FPGA）作为其硬件实现平台，使用Verilog作为该时序设计的编程语言．设计了在其极限频率66MHz下，包含系统校时功能、积分时间可调功能、并行操作功能、多斜率积分功能和NDR（Non-destmctive readout）功能的驱动时序。该设计不仅能产生正确的时序以驱动芯片正常工作．而且充分开发了该器件的辅助扩展功能，大大增加了器件使用的灵活性．有效提高了该传感器的成像品质。经软件仿真和结合硬件平台的测试证明：该设计的正确性和稳定性均满足要求。此时序设计驱动下的探测器芯片动态范围更大、工作更灵活．适合于空间探测，尤其适用于空间暗目标的动态跟踪。