SDH中E3复用/解复用系统的FPGA实现

摘要

E3 multiplexing/demultiplexing system in SDH is designed based on FPGA,including HDB3 coding and decoding,code rates adjustment,mapping/demapping,location/delocation,multiplexing/demultiplexing.Then,function simulation,synthesis,layout and timing simulation are conducted through Quartus Ⅱ 9.0 until the functions have been realized,the designed results are verified by the fourth generation of Altera's Cyclone EP4CE115F29C7N.We use SDH analyzer (ANT-5) to test the designed multiplexing/demultiplexing system,measurement time is one week,the tested results show that our designs are correct.%基于FPGA设计了SDH中E3信号复用/解复用系统,包括HDB3编/译码模块、码速调整模块、映射/解映射模块、定位/解定位模块和复用/解复用模块等.在QuartusⅡ9.0中进行了仿真、综合、布局布线和时序仿真,直至各部分功能分别实现,并在Altera公司的Cyclone第四代产品EP4CE115F29C7N上验证了其正确性.用SDH分析仪ANT-5对设计结果进行了一周的测试,误码为0,说明设计基本正确.