Design of ATM-SDH Multiplex/Demultiplex ASIC

摘要

The combination of ATM and SDH is very important in the future high speed telecommunication network. In our work, we pointed out the need of the low speed ATM transmission through SDH, analyzed the system requirement, planned an ASIC to implement the ATM-SDH multiplex/demultiplex system, designed the chip architecture, described the chip using VHDL coding, and implemented the chip by ALTERA FPGA. Several possible application configuration usign the ASIC and the chip verification system are also introduced in this article.