一种基于EPLL技术的自适应正交解调技术研究

摘要

针对过零检测实现的全数字锁相环不仅锁相速度慢，而且过零点的扰动会直接影响锁相精度以及适合模拟电路实现的相干解调技术，在数字电路中实现则需要设计高阶数字低通滤波器，将占用大量数字电路资源并且会显著增加系统功耗等问题，在设计一种新型全数字锁相环(All-digital Enhanced Phase-lock Loop ， EPLL)的基础上，结合自适应正交解调技术，提出了一种基于EPLL技术的自适应正交解调技术方案，并对该方案进行了研究与仿真。仿真得到了满意的结果，验证了基于EPLL技术的自适应正交解调技术方案的可行性，并研究验证了算法的参数变化对其性能的影响，为今后算法在数字系统中的实现以及其在各领域的应用研究奠定了坚实的基础。%The all-digital phase-locked loop(ADPLL) achieved by using zero-crossing detection technology not on-ly has slow lock-in speed but also its lock-in precision will be directly affected by the zero-crossing disturbance. Further-more, coherent detection technique generally used for amplitude detection is suitable for realization using analog circuits. It will take up a large number of digital resources and significantly increase the power consumption of the system that a high-order digital low-pass filter needs to be designed for the implementation of coherent detection by digital circuits. In order to solve these problems, a new all-digital enhanced phase-lock loop (EPLL) is devised and based on that a new adaptive quadrature demodulation technology (AQDT) program combing EPLL and AQDT is proposed, researched and simulated. The satisfactory simulation results prove the feasibility of the program and verify the parameter changes on the performance of this algorithm that lays the foundation for the further implementation of it in a digital system and its application research in all fields.