基于FPGA的高速数据采集卡的设计

摘要

介绍一种采用USB 2.0接口与PC机进行数据传输的高速数据采集卡的设计.给出了硬件的基本结构和软件固件设计的基本方法,并对用FPGA设计FIFO做了重点阐述,同时对使用异步并行A/D转换与使用采样率为444～440 MS/s的ADC器件的采样数据在FIFO内的数据传输进行了时序仿真,并分析了仿真结果.%A design method of high-speed data acquisition card which uses USB 2. 0 interface and PC for data transmission is introduced. The basic structure of hardware and the basic method of software firmware design are presented. FIFO design based on FPGA is elaborated eaphatically. Moreover, asynchronous parallel A/D conversion and sampling data transmission within the FIFO through ADC device whose sampling rate is 40 MS/s are employed to carry out the timing simulation. The simulation results are analyzed in the paper.