In order to realize wide-band high-performance Sigma-Delta modulator at low oversampling ratio, a 2-1-1 structure with a single-bit quantizer in the front two stages and with a 4-bit quantizer in the final stag is adopted. The influence of nonideal factors (such as clock jitter, thermal noise, operational amplifier finite DC gain) on modulator performance is discussed. The nonlinearity caused by the multi-bit digital-to-analog converter (DAC) mismatching in the feedback loop in the last stage is described emphatically. The date weighted averaging (DWA) algorithm for linearization is adopted to restrain the nonlinearity. The behaviour models including ideal and nonideal models were simulated with Simulink. The results show that the signal-to-noise ratio (SNR) can reach 90 dB, while the sampling frequency is 35. 2 MHz and the oversampling ratio is 16.%为了在低过采样率下实现大带宽、高精度的∑-△调制器,文中采用了级联2-1-1结构,前两级用一位量化器,在最后一级采用4位量化器.讨论了调制器中时钟抖动、热噪声、运放有限直流增益等非理想因素对调制器性能的影响.重点考虑最后一级反馈回路中多位DAC失配引起的非线性,并采用DWA算法对其进行线性化.在Simulink环境下对调制器做行为级仿真,包括理想与非理想模型.在16倍过采样率、35.2 MHz采样频率下,可以达到90 dB的信噪比.
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