The hardware platform of DRFM was studied and designed. A DRFM system implementation scheme is pro-posed,which takes FPGA+ADC+DAC as its core. According to the top-to-down design principle,the implementation process of the hardware system from top layer architecture to bottom layer circuit is introduced in detail,and hardware circuit design of each functional module is analyzed in detail. The hardware system of DRFM was tested. The test results show that the spurious level is only -70 dBc when the bandwidth of the DRFM system is 1.2 GHz and the frequency of input signal is within 100 MHz~1.2 GHz,the system can simulate the radar echo signal,and realize the anticipated effect.%针对宽带数字射频存储器(DRFM)的硬件平台进行研究与设计.首先提出了一种基于FPGA+ADC+DAC为核心的DRFM系统实现方案.然后根据自顶向下的设计原则,详细介绍了硬件系统从顶层架构到底层电路的实现过程,并对系统各功能模块的硬件电路设计进行了详细的分析.最后,对DRFM的硬件系统进行了测试,实验结果表明,该DRFM系统在1.2 GHz带宽,输入信号频率在100 MHz~1.2 GHz范围内,杂散电平仅为-70 dBc,可以进行雷达回波信号的模拟,达到了预期的效果.
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