基于嵌入式方法的浮点单元验证系统设计

摘要

The verification of floating point unit is a big challenge. Based on Xilinx FX series FPGA which have powerpc405 hardcore embedded in it, use embedded system develop tool EDK, design an embedded system to verify floating point unit. The principium is through APU controller link user ip (the floating point unit under verification) to powerpc 405 core, write test program, through user defined instruction to access user ip, according to the instruction result we can know whether the floating point unit can function correctly in real circuit.%浮点单元的验证是最具挑战性的任务之一.基于Xilinx FX系列带powerpc 405硬核的FPGA,利用嵌入式系统开发套件EDK,设计了一个嵌入式系统对浮点单元进行验证.验证原理为把用户IP(被测浮点单元)通过APU控制器连接到powerpc 405处理器核,编写测试程序,通过自定义指令对用户IP进行访问,根据程序的运算结果判断被测IP的正确性.