提出了一种基于FPGA的连通域标记电路设计方案.该方案不仅满足了实时、高精度等要求,还特别增加了虚警剔除的功能.该硬件设计方案采用单次逐像素扫描法,该法通过对图像进行一次逐像素扫描,将标记与参数并行处理,最后根据统计出来的连通域及参数信息实现虚警剔除.相比较其它的硬件实现方案,该设计方案具有显著优势,通过优化标记与参数处理,该方案更适合硬件的并行处理特性；去除了第二次逐像素扫描,使得处理时间变短,资源占用率变小.仿真结果表明:若图像大小为M×N,临时标记区域上限为L,则标记完一幅图像总时钟周期为(M×N×2+L×4).该方案已在单片Virtex-Ⅱ系列FPGA中实现,并作为关键电路应用于舰船图像检测系统中.%A hardware scheme for connected component labeling circuit based on FPGA is proposed in this paper. It not only meets the real-time, high accuracy requirements, but also increases a particular false alarm removing section. A pixel-by-pixel single scanning method is applied in this program, this method carries out a pixel by pixel image scanning, and while achieving the labels processing parallels in time to the parameters processing section, then according to the statistical information, removed false-alarm regions. Compared to other hardware implementation project, this scheme has its significant advantages, by optimizing labels and parameters organizing section, it is more in line with parallel processing features of hardware; time and memory consumption are reduced through removing the second scan process. Simulation results demonstrates that the total cycle of clocks for labeling a image is (MxNx2+Lx4) , if the image size is MxN, the maximum temporary regional labeling is L. This method is implemented on a single VIRTEX- II series FPGA and has been applied to a ship detection system as a critical module.
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