基于分段多项式的直接数字频率合成器设计

摘要

In order to enhance the performance of direct digital frequency synthesizer( DDS), a new technique to implement a DDS with the phase-to-amplitude conversion block using piecewise-polynomial approximation was presented. A design was presented to achieve in the popular field-programmable gate array( FPGA) platform. The hardware was tested, an Altera FPGA prototype implementation results were summarized , the performance and resource consumption were compared with the approach of the ROM lookup table architecture. The experimental results show that this approach achieves better performance, and it reduces the circuit area through avoiding huge loopup table.%为提高直接数字频率合成器( DDS)系统的性能,将分段多项式逼近算法应用于优化相幅转换电路中,实现了基于此结构的直接数字频率合成器设计.提出了适合在流行的现场可编程门阵列( FPGA)平台上实现的电路结构方案,进行了硬件实验,给出了在Altera Cyclone Ⅱ器件中的实现结果,并在性能和资源消耗方面与基于ROM查找表的方案作了比较.研究结果表明,由于避免了庞大的查找表,这一方案大大减小了电路面积,提高了系统性能.