高性能低存储的2维离散小波变换架构

摘要

针对JPEG2000中的5/3小波和9/7小波存在的高存储问题,通过改进离散小波变换(DWT)的提升算法,提出了一种统一的高性能、低存储的2维离散小波变换架构.采用该算法实现的2维离散小波变换架构不仅省去了行列模块间的转置缓存,而且减小了片内缓存的大小.对于N×N大小的图像(N为图像宽度)进行5/32维DWT仅需要2N大小的片内缓存,进行9/7 2维DWT仅需要4N大小的片内缓存,而且通过采用流水线技术还可将关键路径缩短为一个乘法器的延时.和已有的2维DWT架构相比,该统一架构具有更低的片内存储器需求和更高的性能.该架构经Verilog HDL描述,并在ModelSim中验证正确.在Ahera Stratix Ⅱ FPGA EP2S60F1024C4中综合的结果显示,对于1 024×1 024大小的图像,需要1 284个ALUT,片内存储器的大小为4 K,最高频率可达172.56 MHz.%A unified high-performance and memory-efficient architecture is proposed to perform 5/3 DWT and 9/7 DWT in JPEG2000 with a novel modified lifting algorithm. By applying the proposed lifting scheme, the transposing buffer between the row processor and the column processor is eliminated, resulting in a reduction of the internal memory requirement For an N ×N image, only 2N internal memory is required for 5/3 DWT and 4N is required for 9/7 DWT to perform 2D DWT with the critical path limited by one multiplier delay by employing the pipeline technique. Compared with the existing 2D DWT architectures, the proposed 2D DWT architecture has the advantage of regular structure, low memory requirement and high system performance. The proposed architecture was described with Verilog HDL language and verified to be correct in ModelSim. It was also synthesized, placed and routed on an Altera Stratix II FPGA EP2S60F1024C4 using Quartus II version 5. 0 toolset The experimental result shows that 1 284 ALUTs are utilized with memory size of 4 K words for 1 024× 1 024 image and the operating frequency can be up to 172. 56 MHz.