VLSI Architecture of Low Memory and High Speed 2-D Lifting-Based Discrete Wavelet Transform for JPEG2000 Applications

摘要

This work presents a low memory and high speed VLSI architecture for 2-D lifting-based lossless 5/3 filter discrete wavelet transform (DWT). The architecture is based on the proposed interlaced read scan algorithm (IRSA) and parallel scheme processing to achieve low memory size and high speed operation. The proposed lifting-based DWT architecture has the advantages of lower computational complexity, transforming signal with extension, and regular data flow, and is suitable for VLSI implementation. It can be applied to real time image/video operating of JPEG2000 and MPEG4 applications. Basing on the proposed architecture, we designed and simulated a 2-D DWT VLSI chip by 0.35um 1P4M CMOS technology. The memory requirement of the N×N 2-D DWT is N and it can operate at 100MHz clock frequency.