基于FPGA和DSP Builder的FIR数字滤波器设计

摘要

针对FIR数字滤波器的基本原理和结构特点,利用DSP Builder软件设计了一个低通的32阶FIR数字滤波器,并对此进行功能仿真,同时将该设计下载到FPGA中进行硬件测试。测试结果表明,采用该方法设计FIR滤波器简单易行,可缩短设计进程,设计出的滤波器性能稳定、可靠,达到了预期目标。%Based on the basic principle and structural characteristics of FIR digital filters,this paper uses DSP Builder software to design low-pass 32nd-order FIR digital filters,and proceeds function simulation,and then downloads the design in FPGA to have hardware test.The test results show that it is easy and simple to design FIR filters by using this method,which may shorten the design process,and the performance of the designed filter is stable and reliable,which reaches the expected goal.