The Design and Simulation of Embedded FIR Filter based on FPGA and DSP Builder

摘要

The aim of this study is to introduce a new way to design an embedded FIR Filter whose parameters can be adjusted easily to meet different need. FIR Filter plays an important role in the digital signal processing which can implement the function such as low pass filter, pass band selection and etc. A 37 steps low pass FIR filter is designed and simulated in DSP Builder and MATLAB by Filter IP Core which can be converted into VHDL file to be used in Quartus Ⅱ and FPGA device as a embedded model quickly and easily. The simulation result shows the FIR Filter meets the requirement of parameters.