高速ADC交叉采样控制器的FPGA实现

摘要

The high-speed ADC time-interleaving sampling controllers with 2-channel or 4-channel were designed. Its sampling rate can be increased to 2 times and 4 times respectively. The CPU can not meet the speed requirements for high-speed ADC,so the paper used FPGA to achieve control. The controller used FPGA-chip PLL to generate sampling clocks with the equal phase difference , the output clock and control signals, and cross-processed the input data from all ADC time-interleaving sampling data, and then outputted high-speed synthesis of the sampling data. The simulation results show that the control algorithm for time-interleaving sampling can be realized.%设计了2通道和4通道高速ADC交叉采样控制器,可以把采样速率分别提高到2倍和4倍.对高速ADC,使用CPU无法满足速度要求,所以使用FPGA实现控制.控制器使用了FPGA片内锁相环产生具有等相位差的采样时钟、输出时钟和控制信号,对输入的ADC交叉采样数据进行交叉处理,然后输出合成的高速采样数据.仿真结果表明,这种交叉采样的控制算法是可以实现的.