基于NiosⅡ的扫描信号发生器IP核设计

摘要

本文根据NiosII嵌入式系统的Avalon总线规范，提出了一种可控震源扫描信号发生器IP核设计的方法，并详细介绍了IP核的硬件和软件设计。该方法采用自定制组件的软、硬件协同设计，实现了起止频率和扫描时长可调的线性升降频正弦扫描信号与频率可调的伪随机扫描信号发生器的IP核设计。通过对该IP核进行验证，证明了其可行性和正确性。%Based on the Avalon Bus specification of Nios II embedded system, this paper presents a vibrator sweep signal （VSG） IP core design approach and introduced the IP eore hardware and software design in detail. Since this design adopts the co-design method of hardware and software for customized components, the VSG IP core with adjustable start-end frequeneies and sweep time linear sine signal and pseudo signal can been aehieved. The IP core was already verified to be feasible and accurate in design by SOPC system.